1. Field of the Invention
The present invention relates to a semiconductor device and to a method of making the same. More specifically, the invention relates to a semiconductor device and to a method of making the semiconductor device whereby the method eliminates process defects in the device that can be caused by misalignment that occurs during the course of forming a selective silicide layer of a highly integrated dyanamic random access memory (DRAM) or an embedded DRAM, where the DRAM cell forming part and the logic forming part are merged. The present invention therefore provides an improved semiconductor device and simplifies the method of making the device.
2. Description of Related Art
While semiconductor devices are becoming more highly integrated, their contact size is becoming smaller and smaller. This causes a problem because the contact resistance of the semiconductor device becomes larger. To prevent this problem, a salicide (self-aligned silicide) process has been developed, which has been applied to produce a logic device as small as about 0.35 .mu.m. The DRAM of a capacitor on a bit line (COB), however, requires a heat cycle treatment after the salicide process. In addition, the DRAM of a COB requires an extremely low junction leakage at the memory cell region thereof. Thus, the salicide process has not been applied to a DRAM due to the relatively weak junction leakage.
A representative example of a low resistance metal commonly used in the salicide process is W-polycide. There is a gate resistance-related problem, however, that limits applying W-polycide to the giga-bit level of the DRAM in which the wire width of a cell gate typically is smaller than 0.2 .mu.m, or to the DRAM embedded with a high density gate logic. At present, if a selective silicide layer needs to be formed, there is a tendency to use low resistance metals such as TiSi or CoSi, or the like.
If a semiconductor device is manufactured by using the salicide process, there may be no problem if a silicide layer is formed over the entire semiconductor device, but there may be a problem if a selective silicide layer needs to be formed in a particular portion of the device. Such a selective silicide layer may need to be formed due to problems in characteristics of the device, and a separate photo etching process may be needed to leave a silicide blocking layer (SBL) at a particular portion of the device. Forming the selective silicide layer in this manner makes the process procedure complicated and difficult.
In this process, a portion of the formed silicide layer should be opened or etched to have a different step coverage of a gate. Thus, there can be difficulties because a critical level of the photo etching process is required in etching the SBL. To take into consideration misalignment that may occur during the course of the photo etching process, margins should be secured at the portion of the formed silicide layer and at both sides of the SBL. Accordingly, there is a lot of active research to make progress in solving these difficulties.
FIGS. 1 through 7 are diagrams illustrating process sequences for forming a selective silicide layer of a conventional semiconductor device in accordance with previously known techniques. With reference to the drawings, the fabricating method of the semiconductor device can be classified into 7 processes, which will be described in more detail below. For example, when fabricating a semiconductor device having a merged DRAM cell forming part and a logic forming part, the processes of forming a silicide layer at a gate electrode and an active area of the logic forming part and a gate electrode of the DRAM cell forming part will be described even though the silicide layer is not formed at the active area of the DRAM cell forming part (particularly, a storage node forming part). Symbols A and B in the drawings represent the DRAM cell forming part and the logic forming part, respectively, of the semiconductor device.
FIG. 1 illustrates a first portion of the process whereby a polysilicon gate electrode 14 is formed on a silicon substrate 10 having gate insulating layers (not shown) and field oxide layers 12, which are used as a mask to ion implant a low concentration of impurities into the substrate 10 to form a lightly doped drain LDD (not shown). Then, a spacer 16 made of a nitride or oxide layer is formed at both lateral walls of the gate electrode 14, and a high concentration of impurities are ion implanted into the substrate to thereby form an active area (not shown), which serves as a source and a drain inside the substrate 10, and is disposed at both edges of the gate electrode 14.
FIG. 2 illustrates forming an insulating layer 18 made of an oxide layer over the entire resultant structure.
FIG. 3 shows a process of coating an anti-reflective layer 20 (hereinafter referred to as ARL) over the insulating layer 18. The ARL 20 is coated over the insulating layer 18 because ultraviolet (UV) rays may diffuse reflectively on the surface of the insulating layer 18 during the course of the photolithographic process that is performed later on during the process. Therefore, without the ARL 20, it may be difficult to obtain a targeted fine pattern SBL of the insulating layer 18 during the later photolithographic process.
As shown in FIG. 4, a photoresist layer 22 is formed on the ARL 20. Then, A predetermined portion of the silicide layer forming part (for example, the upper portion of the gate electrode 14 of the DRAM cell forming part and the upper portion of the gate electrode and the active area of the logic forming part B) will be selectively etched to expose the surface of the ARL 20.
As shown in FIG. 5, the photo-etched photoresist layer 22 is used as a mask to sequentially etch the ARL 20 and the insulating layer, thereby forming a SBL 18a made of an insulating layer 18 under the etched ARL 20. As a result, the surface of the gate electrode 14 of the DRAM cell forming part A and the surface of the gate electrode 14 and the surface of the active area of the logic forming part B are exposed.
FIG. 6 illustrates a process a removing the ARL 20 by a wet cleaning process using an etchant such as hydrofluoric acid (HF), or the like (e.g., etchants of the HF class). As described above, the ARL 20 is removed before formation of the silicide layer. If the silicide layer is formed with the ARL remaining, there will be a lifting phenomenon during the subsequent heat treatment cycle caused by weak, defective adhesion between the ARL and a subsequently deposited metal having a high melting point.
As shown in FIG. 7, a metal having a high melting point, such as Co, Ti, or Ni, is deposited over the entire substrate 10 including the gate electrode 14, the spacer and the SBL 18a, to which a heat treatment cycle then is applied. At this time, at the region where the SBL 18a is removed, silicon and the metal having a high melting point are reacted to form a low resistance metal that makes up the silicide layer 24. On the other hand, at the region where the SBL 18a remains, or where the lateral wall spacer 16 is formed, the silicon and the metal having a high melting point are not reacted together, thereby leaving the metal having a high melting point as a non-reacted metal. Then, the non-reacted metal having a high melting point can be removed to complete the fabricating procedure.
In the process of forming the selective silicide layer of the semiconductor device thus described, there may be several problems as follow:
Firstly, during the etching process to leave a predetermined portion of the SBL 18a, the ARL deposition process is required, and a critical level of photo etching is required. This results in a complicated fabricating operation and an increase in fabricating cost.
Secondly, even if there is no problem at the region over which the silicide layer is formed over the whole surface, as in the logic forming part B, there may be a problem at the region where the silicide layer is selectively formed on the surface of the gate electrode 14, as in the DRAM cell forming part A. This problem results in misalignment and local formation of the silicide layer at the gate electrode 14 or at the source and drain portion of the active area. As these problems worsen due to a decrease in the size of the fine pattern with the increasing tendency of the high integration of DRAM cells, it is urgent that some measures be taken to solve them.
Thirdly, in the course of removing the ARL, a portion of the SBL 18a may be etched together due to a defective etching selection ratio. In the worst case, the SBL 18a cannot perform its original function, thereby causing a defect that the silicide layer may be formed at regions where it should not be formed.